Sangjin Byun 변상진


KakaoTalk_20160821_214430577

 

I am Prof. Sangjin Byun at Dongguk University.

My research area includes analysis and design of analog circuits for sensor and communication ICs.

아날로그 회로를 연구하는 동국대 전자전기공학부 변상진 교수입니다.

 

I am looking for self-motivated graduate students. To join, please contact me by email.

의욕적인 대학원생을 모집합니다. 아래 이메일로 문의하세요.

 

Address: Engineering Building II, #8108, #8130, Dongguk University, 30, Pildong-ro 1-gil, Jung-gu, Seoul, South Korea, 04620

서울시 중구 필동로 1 30, 동국대학교 신공학관 8108, 8130

Email: sjbyun@dongguk.edu

Tel: 82-2-2260-3331


Research Area

 

[6] Temperature sensor IC: time domain architecture

 

diephoto color setup

 

[5] Fruits sugar content test IC: low noise TIA, multivariate linear regression

 

diephoto TOP4 BOTTOM6

 

[4] Buck converter: sleep control

 

확대 color PCB_color

 

[3] Spread spectrum clock generator: hybrid oscillator

 

CSSIM IMG_0074 diephoto_color pcbphoto_color

 

LJSSCG_PROPOSED pcb2

 

[2] Serial interface IC: referenceless CDR, linear PD, CTLE

 

rx14_color rx11_color usb_color

 

color board2 cdr7 color

 

serdes_rev1 copy CDR CDR_rev CDR_testsetup

 

[1] Bluetooth transceiver IC: time domain GFSK demodulator, accurate RSSI, Gm-C filter

 

color2 color


Graduate Students and Alumni

 

[5] 박유미, Yoomi Park, MS. student

 

[4] 허지위, 志偉, Zhiwei Xu, MS. 2020, @ GigaDevice, China

 

[3] 황종일, Jongil Hwang, MS. 2012, @ Samsung Electronics

 

[2] 심창수, Chang Soo Shim, MS. 2011, @ Samsung Electronics

 

[1] 손충환, Chung Hwan Son, MS. 2011, Ph.D. 2017, @ Siliconworks

 

Undergraduate Students and Alumni

 

[1] 박상우, Sangwoo Park, BS. student


International Journals

 

[23] S. Byun, “Categorization and characterization of time domain CMOS temperature sensors,” Sensors, vol. 20, no. 22, p. 6700, Nov. 2020.

 

[22] S. Park and S. Byun, “A 0.026mm2 time domain CMOS temperature sensor with simple current source,” Micromachines, vol. 11, no. 10, p. 899, Sept. 2020.

 

[21] Z. Xu and S. Byun, “A poly resistor based time domain CMOS temperature sensor with 9b SAR and fine delay line,” Sensors, vol. 20, no. 7, p. 2053, Apr. 2020.

 

[20] S. Byun, “More discussions on intrinsic frequency detection capability of full-rate linear phase detector in clock and data recovery,” Electronics, vol. 7, no. 6, p. 93, Jun. 2018.

 

[19] C. H. Son and S. Byun, “On frequency detection capability of full-rate linear and binary phase detectors,” IEEE Trans. Circuits and Systems-II, vol. 64, no. 7, pp. 757-761, Jul. 2017.

 

[18] S. Byun, “Analysis and verification of DLL-based GFSK demodulator using multiple IF-period delay line,” IEEE Trans. Circuits and Systems-II, vol. 64, no. 1, pp. 6-10, Jan. 2017.

 

[17] C. H. Son and S. Byun, “A 82.5% power efficiency at 1.2mW buck converter with sleep control,” IEIE Journal of Semiconductor Technology and Science, vol. 16, no. 6, pp. 842-846, Dec. 2016.

 

[16] S. Byun, “A 400Mb/s-2.5Gb/s referenceless CDR IC using intrinsic frequency detection capability of half-rate linear phase detector,” IEEE Trans. Circuits and Systems-I, vol. 63, no. 10, pp. 1592-1604, Oct. 2016.

 

[15] S. Byun, “1-3GHz VCO with rail-to-rail VCONT range,” IEICE Electronics Express, vol. 13, no. 11, pp. 20160373, Jun. 10. 2016.

 

[14] S. Byun, “0.97mW/Gb/s, 4Gb/s CMOS clock and data recovery IC with dynamic voltage scaling,” IET Circuits, Devices & Systems, vol. 10, issue 3, pp. 220-228, May. 2016.

 

[13] S. Byun, “Closed-form equation of data dependent jitter in first order low pass system,” The Scientific World Journal, vol. 2014, Article ID 694178, 11 pages, Oct. 16. 2014.

 

[12] S. Byun, “Analysis and design of CMOS received signal strength indicator,” IEEE Trans. Circuits and Systems-I, vol. 61, no. 10, pp. 2970-2977, Oct. 2014.

 

[11] S. Byun, C. H. Son, J. Hwang, B.-H. Min, M.-Y. Park and H.-K. Yu, “1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector,” IET Circuits, Devices & Systems, vol. 7, issue 3, pp. 159-168, May. 2013.

 

[10] S. Byun, C. H. Son and J. J. Kim, “Simple odd number frequency divider with 50% duty cycle,” IEICE Electronics Express, vol. 9, no. 15, pp. 1249-1253, Aug. 8. 2012.

 

[9] J. J. Kim, C.-H. Cho, K.-Y. Chae and S. Byun, “A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications,” IEICE Electronics Express, vol. 8, no. 20, pp. 1730-1735, Oct. 25. 2011.

 

[8] S. Byun and J. H. Shim, “Charge pump circuit with wide range digital leakage current mismatch compensator,” IEICE Electronics Express, vol. 7, no. 23, pp. 1709-1713, Dec. 10. 2010.

 

[7] S. Byun and C. H. Son, “Digital frequency modulation profile for low jitter spread spectrum clock generator,” Electronics Letters, vol. 46, issue 16, pp. 1108-1110, Aug. 5. 2010.

 

[6] S. Byun, “Spread spectrum clock generator with hybrid controlled oscillator,” Electronics Letters, vol. 45, issue 23, pp. 1146-1147, Nov. 5. 2009.

 

[5] B.-G. Kim, L.-S. Kim, S. Byun and H.-K. Yu, “A 20Gb/s 1:4 DEMUX without inductors and low-power divide-by-2 circuit in 0.13um CMOS technology,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 541-549, Feb. 2008.

 

[4] S. Byun and J. Laskar, “Digitally tuned Gm-C filter with VDD/temperature-compensating DAC,” Electronics Letters, vol. 43, issue 5, pp. 280-282, Mar. 1. 2007.

 

[3] S. Byun, J. C. Lee, J. H. Shim, K. Kim and H.-K. Yu, “A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2566-2576, Nov. 2006.

 

[2] J. Kim, J. Yang, S. Byun, H. Jun, J. Park, C. Conroy and B. Kim, “A four-channel 3.125Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 462-471, Feb. 2005.

 

[1] S. Byun, C.-H. Park, Y. Song, S. Wang, C. Conroy and B. Kim, “A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1609-1618, Oct. 2003.

One of most downloaded JSSC papers in 2003.

 

Domestic Journals

 

[3] 변상진, 심재훈, “I/Q 오차 보정 회로를 갖는 2.5GHz Quadrature LC VCO 설계,” 전자공학회 논문지, 48, SD, 2, pp. 35-43, Feb. 2011.

 

[2] 박성경, 이영재, 변상진, “광통신용 10Gbps CMOS 수신기 회로 설계,” 전기전자학회 논문지, vol. 14, no. 4, pp. 278-285, Dec. 2010.

 

[1] K. Lim, J. Hur, K.-W. Kim, S. Byun, F. Bien, C.-H. Lee and J. J. Kim, “Multi-level out-phasing amplification technology for enhancing efficiency and linearity of linear transmitter,” Telecommunications Review, vol. 20, no. 5, pp. 791-808, Oct. 2010.


International Conferences

 

[10] S. Byun, K.-W. Kim, D.-H. Lee, J. Laskar and C. S. Kim, “A self-calibrated LC quadrature VCO in a current-limited region,” IEEE RFIC Symposium, pp. 379-382, Jun. 2008.

 

[9] K.-W. Kim, S. Byun, K. Lim, C.-H. Lee and J. Laskar, “A 600MHz CMOS OFDM LINC transmitter with a 7b digital phase modulator,” IEEE RFIC Symposium, pp. 677-680, Jun. 2008.

 

[8] J. H. Shim, S. Byun, J. C. Lee, K. Kim and C. S. Kim, “A low power 10Gb/s 0.13um CMOS transmitter for OC-192/STM-64 applications,” in IEEE 50th MWSCAS, pp. 1165-1168, Aug. 2007.

 

[7] S. Byun and C. S. Kim, “Low jitter 1.56GHz PLL clock generator for 3.125Gb/s/ch CMOS serial link transceiver,” in ITC-CSCC 2006, vol. 3, pp. 765-768, Jul. 2006.

 

[6] B.-G. Kim, L.-S. Kim, S. Byun, and H.-K. Yu, “A 20Gb/s 1:4 DEMUX without inductors in 0.13um CMOS,” in IEEE ISSCC, Dig. Tech. Papers, pp. 528-529, Feb. 2006.

 

[5] S. Byun, J. C. Lee, J. H. Shim, K. Kim and H.-K. Yu, “A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector,” in IEEE ISSCC, Dig. Tech. Papers, pp. 338-339, Feb. 2006.

 

[4] J. Yang, J. Kim, S. Byun, C. Conroy and B. Kim, “A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18um CMOS,” in IEEE ISSCC, Dig. Tech. Papers, pp. 176-177, Feb. 2004.

 

[3] C.-H. Park, S. Byun, Y. Song, S. Wang, C. Conroy and B. Kim, “A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator,” in IEEE ISSCC, Dig. Tech. Papers, pp. 95-96, Feb. 2003.

 

[2] T. H. Kim, J. Yang, K. H. Lim, J. W. Kim, J. E. Lee, H. S. Nam, Y. G. Kim, J. P. Kim, S. Byun, K. H. Kim, B. S. Kwon and B. Kim, “16bit DSP and system for baseband/voiceband processing of IS136 cellular telephony,” in ASP-DAC, pp. 49-52, Jan. 1999.

Outstanding design award.

 

[1] T. H. Kim, J. Yang, K. H. Lim, J. W. Kim, J. E. Lee, H. S. Nam, Y. G. Kim, J. P. Kim, S. Byun, K. H. Kim, B. S. Kwon and B. Kim, “MIGHTI: a high performance 16bit DSP for mobile communication applications,” in ESSCIRC, pp. 184-187, Sept. 1998.

 

Domestic Conferences

 

[4] 허지위, 변상진, “N 폴리 저항 기반의 시간영역 CMOS 스마트 온도센서,” 대한전자공학회 추계학술대회, pp. 121-123, Nov. 2019.

 

[3] 심창수, 변상진, “0.046UI 지터와 ±1% 변조 비율을 갖는 1.5GHz 스프레드 스펙트럼 클럭발생기,” 18 한국반도체학술대회, TD2-4, pp. 83-84, Feb. 2011.

 

[2] 손충환, 심창수, 변상진, “하이브리드 조정 오실레이터를 이용한 디지털 직접 변조 방식의 스프레드 스펙트럼 클럭 발생기의 설계,” SoC 학술대회, P4.6, pp. 332-335, May. 2010.

 

[1] 변상진, 유현규, “저전력 10Gb/s 클럭 데이터 복원회로의 설계 측정,” 13 한국반도체학술대회, vol. 2, pp. 965-966, Feb. 2006.


Patents

 

[33] 변상진, “클럭 데이터 복원 회로

KR 1756098 B1, Jul. 4. 2017.

 

[32] S. Byun, “Clock and data recovery circuit”

PCT/KR2016/014117, Dec. 2. 2016.

변상진, “클럭 데이터 복원 회로

KR 1725335 B1, Apr. 4. 2017.

 

[31] 변상진, “ 컨버터

KR 1574300 B1, Nov. 27. 2015.

 

[30] S. Byun and C. H. Son, “Buck converter with high power efficiency”

US 10084377 B2, Sept. 25, 2018.

변상진, 손충환, “ 컨버터

KR 1634273 B1, Jun. 22. 2016.

 

[29] 변상진, “클럭 데이터 복원 방법 장치

KR 1576649 B1, Dec. 4. 2015.

 

[28] S. Byun, “Method and apparatus for controlling supply voltage of clock and data recovery”

US 9300303 B2, Mar. 29. 2016.

변상진, “클럭 데이터 복원 회로의 전원 전압을 제어하는 장치 제어하는 방법

KR 1445360 B1, Sept. 22. 2014.

 

[27] 변상진, “비적층적 대칭적 전류모드 논리회로

KR 1428027 B1, Aug. 1. 2014.

 

[26] 변상진, “대역폭이 제한된 채널에서 데이터 의존성 지터 추정 방법

KR 1379371 B1, Mar. 24. 2014.

 

[25] 변상진, “패스 트랜지스터 이를 포함하는 50% 듀티 싸이클을 갖는 홀수 주파수 분주기

KR 1292767 B1, Jul. 29. 2013.

 

[24] 변상진, “바이너리 위상 검출기를 포함하는 클럭 데이터 복원 회로

KR 1211113 B1, Dec. 5. 2012.

 

[23] S. Byun, C. H. Son and C. S. Sim, “Apparatus and method for generating low jitter spread spectrum clock”

PCT/KR2010/005789, Aug. 27. 2010.

변상진, 손충환, 심창수, “ 지터 특성을 갖는 스프레드 스펙트럼 클럭 발생 장치 방법

KR 1136948 B1, Apr. 9. 2012.

 

[22] 변상진, “수신 신호 세기 검출 회로

KR 0971012 B1, Jul. 12. 2010.

 

[21] S. Byun, “Clock and data recovery circuit”

PCT/KR2010/005876, Aug. 31. 2010.

US 8699649 B2, Apr. 15. 2014.

변상진, “클럭 데이터 복원 회로

KR 0989848 B1, Oct. 19. 2010.

 

[20] S. Byun, J. H. Shim and H.-K. Yu, “PSK demodulator using time-to-digital converter”

US 7994851 B2, Aug. 9. 2011.

변상진, 심재훈, 유현규, “타임투디지털컨버터를 이용한 위상 편이 복조기

KR 0976625 B1, Aug. 11, 2010.

 

[19] S. Byun, K.-W. Kim, K. Lim, C.-H. Lee, H.-S. Kim and J. Laskar, “Digital linear amplification with nonlinear components (LINC) transmitter”

US 7889811 B2, Feb. 15. 2011.

Finland 20085820 D0, Sep. 3. 2008.

France 2920925 A1, Mar. 13. 2009.

Germany 20080045570 A1, Apr. 23. 2009.

UK 2452631 A, Mar. 11. 2009.

China 101383641A, Mar. 11. 2009.

변상진, 김관우, 임규태, 이창호, 김학선, Joy Laskar, “디지털 링크 송신기

KR 1004946 B1, Dec. 28. 2010.

 

[18] S. Byun, C.-H. Lee, H.-S. Kim and J. Laskar, “LC quadrature oscillator having phase and amplitude mismatch compensator”

US 7595700 B2, Sept. 29. 2009.

Finland 20085873 D0, Sept. 17. 2008.

France 2921526 A1, Mar. 27. 2009.

Germany 20080048061 A1, May. 20. 2009.

UK 2453046 B, Feb. 3. 2010.

China 101394150 A, Mar. 25. 2009.

변상진, 이창호, 김학선, Joy Laskar, “위상 진폭 불일치 보상기를 갖는 LC 직교 발진기

KR 1101508 B1, Dec. 26. 2011.

 

[17] 변상진, 심재훈, 김천수, “디지털 방식으로 누설전류를 보상하는 전하 펌프 회로 이를 구비한 튜닝 회로

KR 0793318 B1, Jan. 3. 2008.

 

[16] S. Byun and C. S. Kim, “Quadrature voltage controlled oscillator”

US 2008/0079504 A1, Apr. 3. 2008.

변상진, 김천수, “쿼드러쳐 전압제어발진기

KR 0825862 B1, Apr. 22. 2008.

 

[15] S. Byun and C. S. Kim, “LC quadrature VCO having startup circuit”

US 7436266 B2, Oct. 14. 2008.

변상진, 김천수, “스타트업 회로가 구비된 4위상 전압 제어 발진기

KR 0778338 B1, Nov. 15. 2007.

 

[14] 변상진, 하경수, 김이섭, 김천수, “데이터 속도의 1/4 주파수 클럭을 사용하는 고속의 클럭 데이터 복원 회로 방법

KR 0844313 B1, Jul. 1. 2008.

 

[13] S. Byun and H.-K. Yu, “Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method”

US 7456063 B2, Nov. 25. 2008.

변상진, 유현규, “반도체 집적회로의 전원선 레이아웃 방법 방법을 이용하여 제작된 반도체 집적 회로

KR 0810487 B2, Feb. 28. 2008.

 

[12] S. Byun and H.-K. Yu, “Replica bias circuit”

US 7429874 B2, Sept. 30. 2008.

변상진, 유현규, “리플리카 바이어스 회로

KR 0631049 B1, Sept. 26. 2006.

 

[11] S. K. Park, S. Byun and H.-K. Yu, “Adaptive analog equalizer and digital signal receiver having the same”

US 2007/0053419 A1, Mar. 8. 2007.

박성경, 변상진, 유현규, “적응형 아날로그 등화기 이를 갖는 디지털 신호 수신기

KR 0650670 B1, Nov. 21. 2006.

 

[10] 이영재, 변상진, 곽명신, 유현규, “트랜스포머를 이용한 광수신 장치

KR 0682993 B1, Feb. 8. 2007.

 

[9] S. Byun and H.-K. Yu, “Clock and data recovery apparatus”

US 7751521 B2, Jul. 6. 2010.

변상진, 유현규, “클럭 데이터 복원 장치

KR 0706605 B1, Apr. 5. 2007.

 

[8] S. Byun and H.-K. Yu, “Frequency lock detector”

US 7643598 B2, Jan. 5. 2010.

JP 4122017 B2, May. 9. 2008.

변상진, 유현규, “주파수 검출기

KR 0667154 B1, Jan. 4. 2007.

 

[7] 변상진, “아날로그 보상 기능을 갖춘 디지털 필터 튜닝 회로

KR 0544629 B1, Jan. 12. 2006.

 

[6] 양정식, 김진욱, 변상진, 전현덕, 박정규, 민병준, “루프내 지연 보상 /다운 발생기를 이용한 클럭 복원 회로

KR 0511364 B1, Aug. 23. 2005.

 

[5] J. Yang, J. Kim, S. Byun, H. Kim, H. Jun, J. Park and B. Min, “High resolution multiphase clock generator based on array of delay locked loops”

PCT WO/2004/047293 A1, Jun. 3. 2004.

양정식, 김진욱, 변상진, 김현진, 전현덕, 박정규, 민병준, “어레이 지연-로킹 루프를 이용한 고해상도 위상 클럭발생기 회로

KR 0483825 B1, Apr. 8. 2005.

 

[4] J. Yang, J. Kim, S. Byun, T. Kim, H. Kim, H. Jun and B. Min, “High-speed adaptive equalizer”

PCT WO/2004/025917 A1, Mar. 25. 2004.

양정식, 김진욱, 변상진, 김태성, 김현진, 전현덕, 민병준, “고속 적응 이퀄라이저

KR 0467528 B1, Jan. 13. 2005.

 

[3] S. Byun, C.-H. Park and B. Kim, “FSK demodulator using DLL and a demodulating method”

US 7079600 B2, Jul. 18. 2006.

변상진, 박찬홍, 김범섭, “지연 동기 루프를 이용한 디지털 주파수 편이 복조기 복조 방법

KR 0431716 B1, May. 4. 2004.

 

[2] S. Byun, C.-H. Park and B. Kim, “DLL with false lock protector”

US 6844761 B2, Jan. 18. 2005.

변상진, 박찬홍, 김범섭, “오동기 방지기능을 가진 지연 동기 루프 회로

KR 0423012 B1, Mar. 3. 2004.

 

[1] C.-H. Park, S. Byun and B. Kim, “Charge pump circuit for a PLL”

US 6952126 B2, Oct. 4. 2005.

박찬홍, 변상진, 김범섭, “위상 동기 루프용 충전 펌프 회로

KR 0423011 B1, Mar. 3. 2004.


Awards

 

[6] Best poster award, Chip design contest, International SoC Design Conference (ISOCC), Oct. 2016.

“A 82.5% power efficiency at 1.2mW buck converter with sleep control”

C. H. Son, S. Byun

 

[5] Best demo award, Chip design contest, International SoC Design Conference (ISOCC), Nov. 2015.

“4Gb/s, 0.97mW/Gb/s CMOS CDR IC with DVS”

C. H. Son, S. Byun

 

[4] Best demo award, Chip design contest, International SoC Design Conference (ISOCC), Nov. 2013.

“A 5.6Gb/s CMOS CDR IC with a static phase offset compensated linear phase detector”

C. H. Son, S. Byun

 

[3] Outstanding paper award of the year, ICCL, Electronics and Telecommunications Research Institute (ETRI), Apr. 2007.

“A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector”

한국전자통신연구원, 융합부품소재연구소, 올해의 우수논문상, 2007.4.

S. Byun, J. C. Lee, J. H. Shim, K. Kim and H.-K. Yu

 

[2] Commissioner of patents award, Semiconductor circuit design contest, Korea intellectual property office (KIPO), Dec. 2006.

“10Gb/s CMOS CDR/DEMUX IC for SONET OC-192”

7 반도체설계 공모전, 특허청장상, 2006.12.

변상진, 심재훈

 

[1] Outstanding design award, University LSI design contest, ASP-DAC, Jan. 1999.

“16bit DSP and system for baseband/voiceband processing of IS136 cellular telephony”

T. H. Kim, J. Yang, K. Lim, J. Kim, J. E. Lee, H. S. Nam, Y. G. Kim, J. P. Kim, S. Byun, B. S. Kwon and B. Kim